Silicon foundry Silterra ready for 110nm pilot production using CMOS logic technology

Silterra Malaysia Sdn. Bhd., a Malaysia-based wafer foundry provider, has announced the official debut of copper-based 110nm CMOS logic technology. Codenamed CL110G, Silterra's 110nm CMOS process applies a 10% linear optical shrink on its copper-based 130nm node.

Silterra's CL110G technology features eight layers of dual damascene copper metalization, borderless contacts and vias with FSG inter-metal dielectric. The technology is supported by a set of foundry foundation IP from silicon IP providers including Virage Logic and ARM, according to Silterra. The design flow is also validated in Synopsys and Mentor Graphic platforms.

"Customers could take advantage of the new CL110G platform to squeeze extra dies per wafer with uncompromised device performance. Customers will gain about 19% extra die per wafer with reference to pure digital 130nm CMOS Logic design. CL110G is now ready for customer prototypes and we are excited by the level of enthusiasm from our customers all over the world," said Yit Loong Lai, Vice President of Worldwide Sales & Marketing at Silterra, adding "In the current economic downturn, consumers are more cost conscious but their appetite for high performance and low power handheld gadgets remains high."

source